The present invention relates to a method for manufacturing semiconductor devices and, more particularly, to a method for manufacturing a semiconductor device which is capable of preventing pattern shift caused by the reflow of a glass layer during subsequent thermal processes.
There has been great progress in the field of integrated circuit (IC) fabrication, with the trend having been to reduce the size of semiconductor devices. In addition, multiple layers of interconnections between devices, such as ULSI (ultra large scale integration) devices, are now used. A subsequent layer is generally formed on an underlying layer. In order to achieve a better topography, a planarization process is quite often used to obtain a planar surface. Thus, planarization is the key way to make sure that a layer has a planar surface. If one of the multiple layers has poor topography, then this results in alignment problems for subsequent layers.
Typically, during the formation of ICs, a glass layer, such as a borophosphosilicate glass (BPSG) layer, is used as an interlayer dielectric. The BPSG layer is applied in liquid form and therefore exhibits good planarization capabilities. The BPSG layer is also a silicon oxide layer, with specific concentrations of SiO2, B2O3 and P2O5, and is formed by the silicon oxide layer deposition process to which are added dopant gases, such as phosphine(PH3) and diborane(B2H6).
As the integration of devices is increased, not only are cell regions reduced, but the design rule of a periphery region is also reduced. Therefore, various problems are newly generated in sub-micron devices. For example, conducting patterns, which are formed on the BPSG layer in the periphery region, are moved during the BPSG layer reflow process.
Referring to FIG. 1, a conducting pattern 14 formed on a first BPSG layer 100 is shifted, because the first BPSG layer 100 is reflowed in respective thermal steps of depositing and reflowing a second BPSG layer 200 and a third BPSG layer 300. As a result of the reflowing, the conducting pattern 14 may come in contact with a tungsten plug 15, which is exposed on a sidewall of a contact hole. In FIG. 1, The reference numeral xe2x80x9c11xe2x80x9d denotes a gate electrode, xe2x80x9c12xe2x80x9d denotes insulating spacers, xe2x80x9c13xe2x80x9d denotes an interlayer insulating layer, and the reference numeral xe2x80x9cSxe2x80x9d denotes a topological variation caused by the reflow of the first BPSG layer 100 in the thermal processes, such as the respective steps of depositing and reflowing the second BPSG layer 200 and the third BPSG layer 300.
If the conducting pattern 14 is made of a silicide, the conducting pattern 14 is shrunk during the thermal process because the volume of a silicide layer is reduced to 98% at the temperature 800xc2x0 C. As a result, the extent of the shift is increased.
The first BPSG layer 100 is more excessively reflowed in a region where the topological difference is high. Therefore, an unintended interconnection between conducting patterns is generated.
FIG. 2 shows the shifting distance of conducting patterns on a first BPSG layer both in a cell region and a periphery region after a subsequent reflowing process. As shown in FIG. 2, the shifting phenomenon was not observed in the cell region, but only in the periphery region, depending on the topological difference. After the full reflowing process, the shifting distance of the conducting pattern on the first BPSG layer was greater than 0.3 xcexcm.
The conventional method to prevent the reflowing of the first BPSG layer during subsequent thermal processes is to form a TEOS(tetraethylortho silicate) layer having more thermal stability on the BPSG layer. However, the conventional method cannot effectively prevent the shift of the conducting pattern.
It is, therefore, an object of the present invention to provide a semiconductor device formation method for preventing pattern shift caused by the reflow of a BPSG layer in subsequent thermal processes.
In accordance with an aspect of the present invention, there is provided a method for manufacturing a semiconductor device having multiple layers, by using silicate glass layers for planarizing, comprising steps of a) preparing a substrate provided with lower structures; b) forming an insulating layer over the substrate, wherein the insulating layer is not flowed at reflow temperature of the glass layers; c) forming a first silicate glass layer on the insulating layer; d) selectively removing the first silicate glass, wherein parts of the insulating layers are exposed; and e) forming conducting patterns on the insulating layer in such a way that the conducting patterns are directly contacted with the parts of the insulating layer.